Neutron-Induced Pulsewidth Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain-Based Test Structure

This work presents measured data showcasing neutron-radiation-induced single-event transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulsewidth distributions. The SET pulsewidth distributions are obtained from a high-density, array-based characterization vehicle, implemented in 65-nm planar CMOS and 16-nm FinFET processes, featuring a tunable, high-resolution pulse shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro uses standard logic gate chains in varying lengths, threshold voltages (
$V_{\mathrm {TH}}$
), and transistor width flavors as the devices under test (DUTs). The measured irradiation data for a range of operating voltages from nominal down to near-threshold reveal the relative impact of the chosen design parameters such as VDD,
$V_{\mathrm {TH}}$
, device width, and the logic chain length and their interplay, impacting the overall soft error susceptibility and the sampled pulsewidth distributions among the different standard gate types.