A Scanning Test System of p/sFEB Based on FPGA XADC for the ATLAS Phase-I sTGC Upgrade

The pad front-end board (pFEB) and the strip front-end board (sFEB) are developed to read out signals from pads, wires, and strips of the sTGC detector for the ATLAS Phase-I Trigger Upgrade. The pFEB is used to gather and analyze pad trigger, and the sFEB is developed to accept the pad trigger to define the regions-of-interest for strips readout. The performance of p/sFEB must be confirmed before it is mounted on the sTGC detector. We present a scanning test system that is designed according to the test items of the p/sFEB. In the test system, a test pulse board is applied to generate different types of signals to the p/sFEB. The PC software and field-programmable gate array Xilinx analog-to-digital converter cooperate to achieve the scanning test of the analog parameter. At present, the system is utilized for the p/sFEB prototype performance test.