SEU and SET of 65 Bulk CMOS Flip-flops and Their Implications for RHBD

Two 65 nm bulk CMOS test chips, each containing several different types of flip-flop chains, are designed and tested. Heavy ion results are given and analyzed across ion LET and in proposed time domain. The single event upset (SEU) and single event transient (SET) performance of various DFFs are compared and discussed, concluding several practical implications for radiation hardening by design (RHBD). The effectiveness of redundant delay filter (RDF) on mitigating SETs is proven by experiment for the first time.