A Dual Module Parallel Readout System Based on 10 Gb TCP/IP Transmission for HEPS-BPIX Detector

A hybrid pixel detector, which will be used in the high energy photon source (HEPS) with Beijing PIXel (BPIX) chips, has been successfully developed to the third-generation HEPS-BPIX3. It is a 2-D imaging detector with pixel size of 150
$\mu \text{m}$
. The BPIX can work at 20 MHz without dead-time, but the frame rate can only reach 200 Hz limited by the 1-Gb/s TCP protocol of the third-generation readout system. The time structure of HEPS makes it possible to study the ultrafast dynamic evolution of crystal structure, even room-temperature data collection of macromolecular crystallography, so the detector needs to have the ability of fast readout to increase the frame rate up to 1 kHz. Based on this, fast readout and transmission bandwidth become crucial issues, meanwhile, the cost of electronics also should be considered. Therefore, a new dual modules readout board (DMRB) based on field programmable gate array (FPGA) was proposed to realize the imaging of 1.5 Mpixels detector without delay at the frame rate of 1.2 kHz, and an innovative 10 Gb TCP/IP firmware was developed to improve bandwidth. This article introduces how to design, implement, and run the whole system in detail from the perspective of DMRB hardware and firmware, and finally gives the performance results of DMRB with through silicon via (TSV) module at 1.2 kHz frame rate.