New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This article presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed in transmitting multibits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver (CBT) and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent of an FPGA high-speed serial transceiver and does not require a clock data recovery (CRD) circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is a mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM-modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with a duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than
$10^{-13}$
.