A Frequency-Tunable Fractional-N PLL for High-Energy Physics Experiments

A frequency-tunable phase-locked loop (PLL) applied in high-energy particle detectors has been developed. To achieve high detection efficiency, high requirements are promoted for an on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An
$LC$
voltage-controlled oscillator (
$LC$
-VCO) is used to generate the local clock. A third-order MASH sigma-delta (
$\Sigma -\Delta $
) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. To further reduce the phase noise (PN), preset and postset binary frequency dividers are employed. In the prototype chip, a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180-nm CMOS process. It costs an area of 1.29 mm2 and a power of 8.1 mW at a 1.8-V power supply. The measured output frequency range is 400–530 MHz with a reference frequency of 25–35 MHz. The rms jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than −61 dBc, and the PN at 1-MHz frequency offset is less than −113 dBc/Hz.