Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology

This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology for the fifth generation (5G) wireless communication. The design adopts a gain-boosting technique that is comprehensively analyzed with a transformer-based stacked-FET power amplifier (PA). Then, the co-design of the transmit/receive (T/R) switch with the PA and low-noise amplifier (LNA) is investigated, and an electrostatic-discharge (ESD)-aware T/R switch incorporating PA circuitry is proposed to leverage the Tx- and Rx-mode performance. Moreover, the robustness of standalone PA and Tx-mode FEM is simulated and experimentally verified. Furthermore, the ground return paths and supply parasitic paths of the adopted single-ended LNA together with the proposed T/R switch are studied, properly simulated, and assessed. Finally, the proposed PA topology is first verified standalone, exhibiting 32-dB power gain (
$G_{p}$
), an 18.2-dBm output 1-dB compression point (OP
_{1 dB}
), and a 31.1% power-added efficiency (PAE) at OP
_{1 dB}
(PAE
_{1 dB}
). Using this PA in the FEM yields a Tx-mode OP
_{1 dB}
/PAE
_{1 dB}
of 16 dBm/19.4%, and an average output power (Pout
_avg
)/PAE of 10.1 dBm/8.3% for a 100-MHz bandwidth 256-QAM single-carrier signal at an error-vector magnitude (EVM) of −30 dB. In the Rx mode, noise figure (NF) and input-referred third-order intercept point (IIP3) are 3.2 and −5.4 dBm, respectively. A 2-kV human-body model (HBM) ESD protection of the FEM is predicted in transient simulations and measured with transmission line pulse (TLP) tests.