A Milliwatt-Level 70–110 GHz Frequency Quadrupler With >30 dBc Harmonic Rejection

This article presents a two-channel 70–110-GHz frequency quadrupler in the GF8HP 0.12-
$\mu \text{m}$
SiGe BiCMOS process. The
$\times 4$
frequency multiplication is based on cascaded frequency doublers with an interstage bandpass filter to reject undesired harmonics. The measured peak output power is −1.5 to 3 dBm at 70–110 GHz, with a worst case harmonic rejection ratio (HRR) of >30 dBc. The chip size is 1.9 mm
²
and consumes 240 mW for the two-channel operation. To the best of our knowledge, this article represents state-of-the-art in terms of bandwidth, output power, and excellent HRR. Application areas include mm-wave multi-channel, mm-wave network analyzers, and wideband sources for radar and imaging systems and reconfigurable E-band radios.