Design of 94-GHz Highly Efficient Frequency Octupler Using 47-GHz Current-Reusing Class-C Frequency Quadrupler

A 94-GHz highly efficient frequency octupler (×8) is presented, which consists of a 47-GHz frequency quadrupler followed by a 94-GHz push-push frequency doubler. To achieve high efficiency, the former adopts the current reusing technique of which transistors are biased to be in the class-C region. In addition, the core transistors and the input-matching network of the latter are optimized simultaneously by using a premade input matching network library, which yields a maximum conversion gain under a given dc power budget. It is implemented with a commercial 65-nm CMOS process, which generates -7.12-dBm output power with 0-dBm input signal, consuming only 1 mW of dc power. It operates in the frequency range from 84 to 98.4 GHz (15.3%) within 3-dB gain variation. The total efficiency (P
_OUT
/(P
_dc
+ P
_IN
)) is 9.69%, which is the highest among those of reported frequency octuplers.