Modeling of Metal-Fill Parasitic Capacitance and Application to On-Chip Slow-Wave Structures

Modern integrated circuit manufacturing processes generally require the insertion of a large amount of metal fill in layout regions of low metal density to reduce manufacturing defects. We present a general, process-independent, and scalable modeling technique for the computation of distributed capacitance of on-chip transmission lines in the presence of metal fill. The technique reduces the complex 3-D problem to a set of 2-D problems and solves using an effective length and an effective dielectric constant approach. We obtain speedups of about 12 fold for solving the set of 2-D reduced problems compared with a 3-D problem. We verify the accuracy of the technique by comparison with electromagnetic simulations in three process technologies and measurements in a 0.18-μm BiCMOS process. The maximum error in self-capacitance and mutual capacitance is <;6% and <;10%, respectively, over a wide range of processes and physical parameters. The rootmean-square error between measured and modeled capacitance is 9.5%. To further demonstrate the effectiveness of our modeling method, we apply it to various transmission-line structures in the presence of floating conductors.