A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture

This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers. The performance improvement of the cascaded phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The cascaded PLL is implemented using a first-stage fractional-N charge-pump PLL followed by a second-stage quadrature dividerless subsampling PLL. The fractional division in the first-stage PLL is implemented using a high-resolution phase mixer for lower quantization noise. Two prototypes of the single-stage PLL and the cascaded PLL were implemented in the 65-nm bulk CMOS process. The 26-32 GHz quadrature cascaded PLL consumes a total of 26.9 mW from 1-V supply and achieves less than 100-fs integrated jitter with -116.2 and -112.6-dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits of -230.58 and -248.75 dB, respectively.