A 57.5–65.5 GHz Phased-Array Transmit Beamformer in 45 nm CMOS SOI With 5 dBm and 6.1% Linear PAE for 400 MBaud 64-QAM Waveforms

This article presents a low-power, high-gain, high-linearity phased-array transmit (Tx) beamformer chip in a 45-nm RFSOI process. An architecture employing a power amplifier with neutralization, a 180° active phase shifter and 11/22/45/90° passive phase shifter result in high linearity and low power consumption. The measured gain is 22 dB with a 3-dB bandwidth of 57.5-65.5 GHz and an OP1dB and OPsat of 7.5-10 dBm and 9.5-11.5 dBm at 57-64 GHz, respectively. A peak power-added efficiency (PAE) of 14.6% and 17.6% at 60 GHz is achieved at P
_1dB
and P
_sat
, respectively. The measured rms phase and gain errors are <; 4° and <; 0.7 dB at 57-64 GHz, respectively. The beamformer chip also has 14-dB gain control with less than 2.8 dB drop in the OP1dB. Complex modulation measurements using a 400 MBaud 64-QAM waveform show an error vector magnitude (EVM) of 5% (-26 dB) at an average power of 5 dBm and with a dc power consumption of only 52 mW, resulting in a linear PAE of 6.1%. Also, 18-20 Gbps data rates are demonstrated with an EVM <; 5% (64-QAM) and <; 9% (16-QAM) at 60 GHz. To the author's knowledge, this work achieves state-of-the-art linearity and efficiency for 60-GHz communication systems.