A New Compact CMOS Distributed Digital Attenuator

This article presents a new millimeter-wave (mm-wave) distributed digital attenuator with a compact size and high linearity. To overcome the large area consumption of conventional distributed attenuators, multiple unit attenuation cells are combined at a single node, forming a multistate cell. By distributing the multistate cells along transmission lines (T-lines), the number of T-lines is reduced, leading to a compact chip size at a given attenuation range and step. The linearity is improved by stacking multiple FET varistors in each unit attenuation cell. An analytical analysis confirms that the proposed distributed attenuator topology maintains a low phase error comparable to that of the conventional counterpart. To experimentally verify the proposed topology, two different mm-wave digital attenuators are designed and implemented using a 65-nm CMOS technology. The first attenuator (Att1) uses a regular nFET as varistor of the attenuation cell, whereas the other attenuator (Att2_TW) uses a triple-well nFET to reduce the insertion loss. The maximum attenuation range of both attenuators is 14 dB with a step of 1 dB. The measured insertion losses of Att1 and Att2_TW are 4.8 and 4.1 dB at 35 GHz, respectively. The insertion losses are no more than 6.2 dB over 10–50 GHz and 4.3 dB over 15–43 GHz, respectively. The input 1-dB compression powers are 15 and 14 dBm, respectively, at 35 GHz. The chip sizes, excluding probing pads, are as small as 0.19 and 0.29 mm
²
.