An Energy Efficient In-Memory Computing Architecture Using Reconfigurable Magnetic Logic Circuits for Big Data Processing

In-memory computing (IMC) is considered one of the most promising candidates to solve the nontraditional challenges conventional computing systems face in dealing with novel big data applications. This article proposes an efficient hybrid magnetic tunnel junction (MTJ)/FinFET base IMC architecture performing all basic Boolean logic operations (AND/NAND, OR/NOR, XOR/XNOR) in only one system clock. To this end, a novel memory cell design based on in-plane anisotropy MTJ (I-MTJ) is proposed, which can perform various logic operations in the memory array. In the proposed array, various logic operations can benefit from connecting I-MTJ memory cells in series in the selected column and a novel sense amplifier (SA) unit. Moreover, the full adder (FA) operation is accomplished by exploiting the Majority logic function, which indicates its functionality mostly in a ripple carry adder (RCA) implementation that requires only
$n$
+ 2 clock cycles for
$n$
-bit calculation. The circuit-level simulations indicate that the proposed design improves energy consumption of performing the AND/NAND and OR/NOR operations by approximately 80%, the XOR/XNOR operations by 79%, and the FA operation by 47% compared to its state-of-the-art counterparts. Moreover, the Monte Carlo simulations authenticate the high robustness of the proposed architecture in the presence of process variations. To validate the proposed design’s efficiency in real-world applications, the minimum/maximum image filters, as the essential preprocessing steps in widely used applications like optical character recognition (OCR) and the VGG-16 neural network with the ImageNet dataset, are implemented using the proposed IMC architecture.