Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-Compatible MTJ Stacks

The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today’s spintronic applications such as magnetoresistive random access memory (MRAM), magnetic sensors, and prospectively as a reading device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desired properties, such as tunnel magnetoresistance (TMR), magnetic anisotropies, or coercive field of the free layer (FL), requires careful optimization of the deposition parameters as well as precise layer thickness control. Here, the deposition of individual layers in a wedged manner across 300 mm wafers is proposed to engineer the thicknesses within the stack more efficiently. Furthermore, this technique provides detailed insights into effects related to surface roughness, magnetic anisotropy, and TMR.