Hardware Efficient Low-Frequency Artifact Reduction Technique for Wearable ECG Device

The wearable/portable electrocardiogram (ECG) devices are helpful for continuously monitoring the heart and early detection of cardiovascular diseases (CVDs). Various low-frequency (LF) artifacts present in the ECG signal create difficulty in ECG interpretation. The traditional artifact reduction methods do not provide a better tradeoff between low-power hardware design and high signal quality. This work provides a better tradeoff by proposing a novel method using a reference-free single tap adaptive filter and lower order moving average (MVA) filter. The proposed method is compared using various popular parameters to check filter performance over the ambulatory ECG Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) arrhythmia database. It provides 18.43% more average signal-to-noise-ratio improvement (ASNRI) and 30.27% higher average mean square error (AMSE) minimization with less distortion than the existing hardware-efficient methods. The multiplier-less hardware architecture has been efficiently designed and implemented on field programmable gate array (FPGA). It occupies only 293 look up tables (LUTs) and consumes
$0.34~\mu \text{W}$
of power at a 500 Hz sampling frequency when implemented on Zynq-7 FPGA. The proposed hardware design takes 21.45% fewer LUTs and 14.97% better signal quality (ASNRI) and 24.15% more AMSE minimization than existing work.