I. Introduction
The evolution of the smart grid has led to a situation in which any improvements to grid resilience and power quality rely on a good control over grid-connected converters (GCCs) [1], [2]. The control architecture of GCCs is composed of well-known grid synchronization algorithms, i.e., phase-locked–loops (PLLs) and frequency locked–loops [3]–[14]. The high performance of a control algorithm is generally achieved by means of analog or digital signal conditioning units. With the pertinent digital signal processors, the robust performance of a control technique relies on the rapid removal of the noise and the harmonic components [4], and there is consequently a need for research into immunity-based digital filtering techniques [5]. The optimized filtering techniques often applied in order to develop better control architecture of GCCs are reported in [6]–[8].