A High-Resolution TDC Design Based on Multistep Fine Time Measurement by Utilizing Delay-Adjustable Looped Carry Chains on FPGAs

High-resolution and multichannel time-to-digital converters (TDCs) are needed in many electrical application systems. A new multistep fine time measurement method is proposed in this work, which is based on the delay-adjustable looped carry chains to obtain both high resolution and measurement precision. Each sub-step of the fine time measurement is assigned with a different measurement resolution in the descending order by dynamically configuring the delay line length. The time residue to be measured in the following sub-step becomes smaller, so that a finer resolution can be chosen. The overall oscillation number is the summation of the oscillation number of each sub-steps. The resolution of the TDC is determined by the last sub-step. So both high-resolution and small oscillation number (corresponding to high measurement precision) can be obtained. The TDC circuit was implemented on Stratix III field programmable gate array (FPGA) chip. Test results showed that the obtained resolution was less than 10 ps, and the measurement precision root mean square (rms) was about 13 ps. The differential nonlinearity (DNL) error and the integral nonlinearity (INL) error were in the range of −1 least significant bit (LSB) to 1 LSB without any bin calibration. The resource cost per TDC channel includes the lookup table (LUT) cost of 1064 and register cost of 318. The obtained TDC is comprehensively good considering its low resource cost and high linearity, and it is promising for multichannel TDC design.