Layout Optimization and Parasitic Reduction in Sub-60-nm nMOSFETs for Super-350-GHz fMAX

Sub-60-nm nMOSFETs with optimized layouts and effective suppression of parasitic resistance–inductance (
RL
) can reach super-350-GHz
${f} _{\text {MAX}}$
and facilitate mm-wave CMOS circuits design aimed at the D-band (110–170 GHz) and even higher to the G-band (140–220 GHz). However, in practice, the complicated layout-dependent effects and tradeoff between various parasitic RLCs become the major bottleneck for achieving the theoretical
${f} _{\text {MAX}}$
and simultaneous optimization of
${f} _{T}$
and
${f} _{\text {MAX}}$
. The mentioned challenges become even worse for four-terminal (4T) multifinger (MF) MOSFETs adapted to various circuit topologies and operation schemes for RF and mm-wave circuits design. In this article, the precise extraction of intrinsic parasitic RLC in 3T and 4T MF nMOSFETs and analytical models derived for
${f} _{T}$
and
${f} _{\text {MAX}}$
can realize accurate simulation and layout optimization guideline for mm-wave CMOS circuits design.