Characterization and Analysis of 4H-SiC Super Junction JFETs Fabricated by Sidewall Implantation

Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of
$1.8 \mu \text{m}$
and active area of 0.104 mm
²
achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98
$\text{m}\Omega \,\cdot $
cm
²
. The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the
${x}$
-direction and trapezoidal mesas in the
${y}$
-direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop (
$\vert {V}_{\text{on}}\vert $
) and the maximum current before gate junction turn-on (
${J}_{\text{umax}}$
). The third-quadrant performance can be improved by using forward-on gate voltage, a
$\vert {V}_{\text{on}}\vert $
lower than 0.2 V (at 100 A/cm
²
) and a
${J}_{\text{umax}}$
larger than 500 A/cm
²
are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications.