Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond

Through a comparative analysis of gate-all-around field-effect transistors (GAAFETs) with the same layout footprint as FinFETs of 3-nm technology nodes, the effect of the tapered fin shape on device performance is determined using the 3-D technology computer-aided design (TCAD) simulation. Moreover, this comparative study presents the most optimal taper angle in terms of various device figures of merits (FoMs) for a standard supply voltage (
${V}_{\text {DD}}$
) of 0.7 V and a low
${V}_{\text {DD}}$
of 0.35 V. Since FinFET of sub-3 nm is most affected by the short-channel effect (SCE), the vertical shape with the best electrostatic control is advantageous for dc and ac performances. On the other hand, in the case of GAAFETs, such as nanowire (NW) and nanosheet (NS), although vertical fin is the lowest dc performance due to the smallest effective width, we confirmed the best ac results due to the impact of capacitance gain. Furthermore, we demonstrated that NWFET and NSFET with straight shapes could achieve more than the frequency gain of
$2.2\times $
and
$1.2\times $
at the same power, respectively, compared to FinFETs in low
${V}_{\text {DD}}$
operation.