Complete Accumulation Lateral Double-Diffused MOSFET With Low ON-Resistance Applying Floating Buried Layer

A novel complete accumulation lateral double-diffused MOSFET with floating buried layers (CA-FBL LDMOS) is proposed to reduce the
${R}_{ \mathrm{\scriptscriptstyle ON}, \text {SP}}$
and improve the breakdown voltage (BV) synchronously. The CA-FBL LDMOS is characterized by n-type floating buried layers (FBLs) and a gate semiconductor layer consisting of two p-n junctions. For CA-FBL LDMOS, the conduction of current completely relies on the accumulated electrons, instead of the doping concentration of the drift region. The conduction mechanism of CA-FBL LDMOS is to change the potential distribution of the gate semiconductor layer and then form an electron channel under the oxide layer. Not only does the density of electrons in the channel increase greatly, but also the channel extends from the source to drain electrodes, and the effective gate length increases. Therefore, the
${R}_{ \mathrm{\scriptscriptstyle ON}, \text {SP}}$
decreases sharply. Thanks to the n-type floating layers, the bulk electric field distribution of the device is also optimized. The electric field crowing at the edge of the drain diffusion region is relieved. The speed that the BV runs to saturation slows down. Moreover, the BV can be further improved by increasing the number of n-type FBLs. The simulation results indicate that the BV of CA-FBL LDMOS is 898 V with the drift region length of 50
$\mu \text{m}$
and the
${R}_{ \mathrm{\scriptscriptstyle ON}, \text {SP}}$
is only 33.8
$\text{m}\Omega \cdot $
cm
²
, which is reduced by 73% compared with FBL lateral double-diffused MOSFET (LDMOS) without accumulation effect. However, affected by the built-in potential of p-n junction in the gate semiconductor layer, the threshold voltage of CA-FBL LDMOS (3 V) is slightly higher than that of FBL LDMOS (1.5 V). At the same time, due to the higher dielectric coefficient of the gate semiconductor layer and the increase of effective gate length, the turn-off time of CA-FBL LDMOS also increases slightly. But compared with the rapidly decreased conduction loss, the switching loss is acceptable.