Demonstration of Geometrical Impact of Nanowire on GaAs1–xSbx Transistor Performance

In this article, we demonstrate the impact of nanowire geometry of GaAs
_1–x
Sb
_x
transistor. Circular, square, and triangular gate-all-around (GAA) geometries are taken to investigate the characteristics of the GaAs
_1–x
Sb
_x
nanowire using a well-calibrated TCAD setup. This work analyzes: 1) the potential and field profiles; 2) the effect of channel mobility on the transfer characteristics (
${I} _{D}$
–
${V} _{G}$
) of all three geometries; 3) trend of the total gate capacitance (
C–V
); 4) impact of interface trap charges; 5) analysis of noise spectral density for each geometrical nanowire; and 6) impact of temperature (down to cryogenic range) on the performance metrics. We found that the equivalent distance from the center-to-surface of the nanowire is relatively small in triangular nanowire (TNW), resulting in a superior subthreshold slope (SS), DIBL, and OFF current. TNW shows ~8.9% (8.7%) and ~76.4% (75%) reduction in SS and DIBL with ~
$61.67\times $
(
$20.1\times $
) improvement in
${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$
ratio as compared to circular (rectangular) nanowires. We have also analyzed the PSD of 1/f noise and noise figure (NF) of each geometrical nanowire and found that TNW has ~5.97% (~10.1%) higher NF than CNW (RNW). Furthermore, we investigated the impact of temperature down to the cryogenic range over the device metrics such as threshold voltage (
${V} _{th}$
),
${I} _{on}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$
, transconductance (
$\text{g}_{m}$
), and so on. Hence, a nanowire geometry can be optimized through the obtained design explorations and could be used for high-performance applications.