Switching Performance Enhancement in Nanotube Double-Gate Tunneling Field-Effect Transistor With Germanium Source Regions

In this article, we introduce a double-gate nanotube tunneling field-effect transistor with high scalability based on the Si/Ge heterostructure. Our device includes two Ge source regions which are covered by the gate metal to facilitate line tunneling in these regions. The tunneling charge carriers flow toward the drain region through two n
⁻
Si channel regions. The manufacturing process of the proposed transistor is fully compatible with CMOS technology. The performance of the device is investigated by employing a numerical simulator which is calibrated to experimental data. We achieved a remarkable switching performance including a minimum subthreshold swing (SS) of 10 mV/dec, an
${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$
ratio of 3.92
$\times 10^{{7}}$
, an ON-state current of 52.19
$\mu \text{A}/\mu \text{m}$
, and a drain-induced barrier lowering of 45 mV/V for the device; moreover, the ambipolar conduction completely vanished.