Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P–V and I–V in HfO₂-Based Ferroelectric FET

The ferroelectric (FE)-HfO
₂
-based field-effect transistor (FEFET) is a promising candidate for emerging memory. However, data retention (DR) loss has been flagged as a key issue. Although two models of DR loss in FEFET have been proposed—the charge trapping model and the depolarization model—it is difficult to separate the dominant cause. In this article, simultaneous
${P}$
–
${V}$
and
${I}$
–
${V}$
measurements are performed which enable separation of these mechanisms. Different behavior of polarization and threshold voltage loss and recovery in a “set” state between two types of FEFET structures, metal (TiN)/FE-HfO
₂
/SiO
₂
/Si substrate (MFIS) and metal (TiN)/Si/FE-HfO
₂
/SiO
₂
/Si-substrate (MSFIS), clarify that the dominant mechanism of the DR loss in both structures is different. In addition, the impact of external bias and interfacial layer (IL) on the DR loss is revealed: the polarization loss is strongly affected by the external bias in both types of FEFET, indicating effective work function (eWF) has a strong impact on depolarization. On the other hand, the thickness and processing of IL strongly impact the charge trapping characteristics. Based on our understanding, excellent improvement of the DR is achieved: memory window ~0.8 V at 85 °C, extrapolated to ten years.