A Surface Potential Model for Field-Effect Transistors With Bound-Charge Engineering

Semiconductor doping is limited by such practical concerns as bandgap narrowing and solid solubility limits of dopants. Bound-charge engineering (BCE) bypasses these limits by doping with surface bound charge located on the interface between a semiconductor and an adjacent low-permittivity oxide; it can be used to reduce depletion lengths of junctions in field-effect transistors (FETs). BCE is established by basic electrostatics and is widely applicable to emerging materials and novel devices. In this work, an analytical surface potential model for gate-all-around BCE-assisted silicon nanowire FETs, with arbitrary and possibly distinct spacer and gate oxides, is derived. This model is based on scaling theory and verified against atomistic quantum transport simulations; it provides an intuitive formalism for developing and modeling devices with BCE.