Degradation Behavior and Defect Analysis for SiC Power MOSFETs Based on Low-Frequency Noise Under Repetitive Power-Cycling Stress

In this article, the degradation behavior of the commercial 1.2-kV SiC power MOSFETs was investigated under repetitive power-cycling stress, and defect analysis based on low-frequency noise (LFN) was carried out. The experimental results show that increasing power-cycling stress results in a forward shift of threshold voltage and increasing ON-resistance. Meanwhile, the drain-to-source current significantly decreases with the increase of the cycles. Furthermore, the gate–source leakage current of the device became larger and the blocking characteristics deteriorated after 10-k cycles. The negative shift of the gate-capacitance versus gate-voltage curve was analyzed. Trap characterization was performed by using the LFN method, and it was found that the trap density of the device increased 5.47 times after 10-k cycles. The physical mechanism could be attributed to electrically active trapped charges generated at the SiC/SiO
₂
interface during power-cycling stress. This article may be helpful for degradation detection and fault analysis of SiC power MOSFETs in the electronic system.