Noise-Immune 6T SRAM Bit-Cells Based on Side-Contacted FED

Modern system-on-chip (SoC) designers are trying to include more considerations in designing building blocks to present reliable integrated digital circuits as well as high-density ones. In this article, an innovative static random access memory (SRAM) bit-cell architecture is successfully designed based on the previously proposed side-contacted field effect diode (S-FED) using 180-nm technology. The device structure is optimized to satisfy high I
_ON
/I
_OFF
ratio more than seven orders of magnitude. Behavioral modeling of S-FED in comparison with CMOS counterpart provides the capability of employing S-FED in the pull-down, pull-up, and pass-gate networks with identical geometry. The simplest triple S-FED-based bit-cell is designed to evaluate write and read logic 0/1 operations utilizing steady-state responses. Transient and ac analysis are also extracted from the six S-FED-based bit-cell to characterize SRAM fingerprints. Results demonstrate that the proposed bit-cell is noise-immune with maximum static noise margin (SNM) equal to 33.6% V
_DD
, high-speed with switching frequency of about 1.8 GHz (write) and 50 MHz (read), and low-power with static and dynamic power consumption lower than 10 nW and 5 nW/GHz, respectively. Moreover, SNM and Monte Carlo (MC) analyses reveal outstanding stability of the designed SRAM bit-cell based on S-FEDs when extreme variability scenarios induce device degradation.