Contents I. Introduction
FinFET technology at 14 nm node is equipped with full suite of analog/radio frequency (RF) features catering to functionalities up-to 3.3 V [1]. However, for advance SoC applications [2], high-voltage (HV) devices with >5 V rating are desired to enable a wider range of functionalities on chip like RF-PA, power management circuits, dc–dc converters, and so on. This gap can potentially be filled by stacking of the medium voltage transistors, which is one of the approach to scale up the voltage handling capability of a design. However, attributed to aggressive scaling in advance CMOS nodes, transistor stacking is not a preferred option due to intrinsic reliability concerns [3]–[5]. Other approach is to enable a HV device using drain extension [6]. Due to its CMOS process compatibility, HV drain-extended MOS devices in the preceding planar nodes have successfully enabled HV (5–20 V) functionalities, which has fueled the advanced SoC development [7]–[10]. Going forward to Fin-based technologies, drain-extended FinFET (DeFinFET) seem a much viable option. However, in a Fin-based technology, drain-extended solutions [11], [12] for HV options have not yet been adapted. Due to thin silicon volume in Fin technology [13], the performance and reliability assurance at higher voltage is questionable [11], [14], [15]. Furthermore, high ON-resistance () caused by the Fins, and Fin technology-based design rules makes the drain extended device design much more challenging [16] than its planar counterpart.
