Simulation Study on the Optimization and Scaling Behavior of LDMOS Transistors for Low-Voltage Power Applications

We present a systematic investigation of device optimization for laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors in terms of subthreshold leakage current, breakdown voltage, and ON-resistance for low-voltage (<; 10 V) power applications. We simulate and optimize n-channel 5-V LDMOS devices in order to reach a target leakage current and breakdown voltage. Device simulations and optimizations are performed by running an optimization algorithm, implemented as a computer code, on top of a commercial drift-diffusion simulation package. We find that n-channel LDMOS devices can realize leakage currents smaller than 10
^-13
A/μm while maintaining a breakdown voltage exceeding 10V for channel lengths down to 10 nm. Interestingly, we find an optimal ON-resistance for a channel length of 40 nm, while for shorter channel lengths the ON-state resistance increases with decreasing channel length. The increasing resistance for shorter channels is caused by electron mobility degradation as a result of an increasing body doping, needed to limit the leakage current. The optimal channel length presents a limit to conventional scaling of LDMOS devices, commonly used in low-voltage power applications.