Investigation and SPICE Compact Model of Spacer Region for Static Characteristics of 3-D NAND Flash Memories

In this article, we present an appropriate compact model of spacer (SP) region for static characteristics of 3-D NAND flash memories. Though many studies on 3-D NAND flash have focused on the intrinsic part, they have not considered analysis on the SP region with gate-surrounded structure which is inevitable for 3-D NAND flash string due to punch-and-plug process. We focus on the electrostatics on the SP region of the 3-D NAND flash and suggest a concept of bias ratio (BR) which can evaluate the average influence of fringing electric field on the parasitic part for efficient implantation to the compact model. First, we introduce the modeling method of the SP region and then verify our modeling results by comparing channel potential using 3-D technology computer-aided design (TCAD) simulation. We also investigate the BR dependences on various device dimensions, and the dependences are comparable with the trends of outer-fringing capacitance. Finally, we demonstrate that our compact model can be efficiently applied to circuit simulation for various bias conditions and varying dimensions such as tapered channel structure, without the necessity of additional parameter extractions for each dimension.