Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure

In this article, structure optimization of high-k interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High-k IL can be formed during the high-k gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high-k IL (T
_hk
) with gate length (L
_G
), spacer length (L
_ext
), and source/drain (S/D) length (L
_S/D
), improved electrical performances were obtained. By optimizing T
_hk
with properly adjusted L
_G
, L
_ext
, and L
_S/D
, highly saturated ON-/OFF-current ratio (I
_ON
/I
_OFF
) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay (C
_gg
) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shown when L
_ext
shrinks with extending T
_hk
, was also investigated. Finally, the optimized electrical characteristics were obtained when T
_hk
is adjusted with L
_G
and L
_S/D
. The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when T
_hk
is optimized through L
_G
. On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with L
_S/D
, which result in lower static power. Based on this comparison, optimization method and guideline for high-k IL was proposed.