True Random Number Generation From Commodity NVM Chips

In this article, we propose a novel technique to generate true random numbers (TRNs) using off-the-shelf non-volatile memory (NVM) chips. In particular, we illustrate a TRN generator (TRNG) extraction methodology from two types of NVM technologies: 1) emerging resistive NVM, and 2) charge-based NOR flash. We exploit the variability in programming latency while performing write and erase operations. The main causes of such effects can be attributed to the switching-time variability of the NVM devices and second-order effects, such as peripheral CMOS variability and circuit parasitics. Through multiple experiments, we show that dominant variability contribution arises from NVM switching-time distributions. In order to increase the quality of randomness, we propose an XOR-based post-processing technique. In the proposed methodology, latency values are first extracted from multiple locations on the chip followed by the application of post-processing technique. The randomness of the generated bitstream is evaluated using NIST SP 800-22 statistical test suite, and all the 15 tests are passed with encouraging P-values. We validated the proposed NVM-based TRNG for a wide range of operational temperatures (-40 °C to +85 °C). Utilization of the existing NVM chips and no requirement of additional specialized hardware make the proposed TRNG technique highly advantageous and cost-effective.

I. Introduction

Random number generator (RNG) is an essential building block for secure data handling systems, stochastic computation, brain-inspired computing, and Monte Carlo simulations. True RNGs (TRNGs) exploit the inherent nondeterministic or chaotic physical phenomena of circuits and devices to generate random bits, making them extremely hard to predict and thus important for cyber-security applications [1], [2]. Several proposals in the literature on TRNG have been demonstrated over the last few years that rely on exploiting different physical processes of nanoelectronic devices/circuits, harnessing inherent physical properties, such as switching behavior, random telegraphic noise (RTN), variability, and stochasticity [3]–[5]. Recently, the generation of random numbers based on semiconductor memory (volatile and non-volatile) has also been explored. TRNG based on static random access memory (SRAM) [6], dynamic random access memory (DRAM) [7], [8], charge-based flash memory [9], and even emerging non-volatile memory (NVM), such as resistive random access memory (RRAM) [10], [11], STT/MRAM [12], and FRAM [13], has been proposed. The memory-based RNGs proposed in the literature exploit multiple phenomena, such as remanence effect of a memory cell [14], memory startup values [15], program disturb [16], RTN and thermal noise [17], switching-time variability, access-time variability [18], and partial programming of memory cells [19]. However, most NVM-TRNG results in the literature are based either on simulations or implemented on a few standalone devices or small arrays [18], [20]. Moreover, most of these NVM hardware TRNGs require analog sensing and additional complex interfacing circuits apart from the NVM arrays [21]. Limited work exists on TRNGs that can be extracted from off-the-shelf commercial NVM chips [9], [19], [22]. The advantages of using off-the-shelf NVM chips for TRNG applications are: 1) ease of implementation, 2) low cost, and 3) reduction of additional complex circuitry. Moreover, the use of off-the-shelf NVM chip for security application expands the utility of the technology from data storage to data security simultaneously. In this article, we present the extraction of true random numbers (TRNs) from two different types of commercially available off-the-shelf NVM chips: 1) emerging resistive NVM [23] and 2) conventional charge-based NOR flash [24]. We primarily exploit the variability in page-write, page-erase, or sector-erase latency. The latency variability is coupled with a post-processing technique that significantly enhances the quality of randomness of the obtained bit streams. Key contributions of this article are as follows: 1)

a generalized methodology for TRNG from NVM chips based on a different underlying working principle without modifying existing memory chip macro;

2)

experimental demonstration of high-quality NVM TRNG over a wide range of operational temperatures.