Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits 1.65×/3.03×/1.08×/1.38× shorter write delay (TWA) and 3.81×/1.20×/1.90×/2.13× higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and 1.36×/1.54×/1.22× shorter read delay (T
_RA
) and 6.63× higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes 1.05×/1.21×/1.10×/1.81× lower static power (H
_PWR
) than that of FD8T/SEDF9T/D12T/WWL12T while showing 3.44× higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes 1.01×/1.02×/1.04× smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of 1.37×/1.13× penalty in T
_WA
/T
_RA
and 6.23× penalty in H
_PWR
when compared to FD8T and BI11T, respectively, at V
_DD
= 0.7 V.