Endurance Statistical Behavior of Resistive Memories Based on Experimental and Theoretical Investigation

Endurance reliability at the array level of resistive random access memories (RRAMs) is addressed. Both oxide based RAM and conductive bridge RAM stacks are extensively characterized, presenting various measurements over resistive layers, memory stacks, and programming conditions. These measurement results allow to extract the maximum number of cycles before breakdown N
_cmax
. It is found that this quantity follows a log-normal law. According to this first significant result, the impact of SET and RESET conditions on N
_cmax
statistics is studied. Using tailored ramp voltage stress (RVS) measurements, the minimum RRAM switching voltage is extracted along the endurance cycles and then correlated with the memory degradation. To explain and better understand all these experimental results, a stochastic model based on defect generation in a constriction zone of the resistive layer during cycling is proposed. After exploration of the size, geometry, and shape of such constriction zone, as well as different probability laws governing breakdown, modeled N
_cmax
distributions fitting the experimental ones are successfully generated and deeper explanations about the origin of the maximum number of cycles variability are inferred.