A Novel Twofold Tunnel FET With Reduced Miller Capacitance: Proposal and Investigation

A novel twofold tunnel field-effect transistor (TF-TFET) is proposed and investigated for the first time in this paper. The physical characteristics and digital applications of the TF-TFET are demonstrated with rigorous simulation by using Sentaraus TCAD. The proposed TF-TFET is an admixture of both n- and p-type TFETs, and hence, this single device acts as an inverter. It helps to reduce the transistor count in the digital/analog applications. The impact of various device parameters on its performance has been studied extensively. The advantageous factor of the proposed TF-TFET is the presence of an additional capacitance at the drain junction, which helps to reduce the overall Miller capacitance. Moreover, the voltage transfer characteristics (VTC) and transient behavior of the TF-TFET inverter along with some standard cells like XOR gate and 2:1 MUX have been explored using mixed-mode simulation.