High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime

In this paper, we investigate the impact of spacer dielectrics on the ultrascaled silicon gate-all-around junctionless transistor in the ballistic regime based on the in-house 3-D quantum simulator that self-consistently solves mode-space nonequilibrium Green function formalism and Poisson's equation. Then, the impact of device parameters, such as lengths of source/drain region and channel, channel width, and nanowire direction, on the static performance is also discussed in detail. An available range of spacer dielectric constant is further selected. Results show that the high-k spacer introduced in the ultrascaled junctionless transistor can effectively enhance the direct-current performance of the device and suppress the variation of drain current and subthreshold characteristics induced by the aforementioned device parameters. It will be a great benefit for the junctionless device with a gate-all-around structure as the scaling continues to approach the end of MOSFETs.