Self-Amplified Tunneling-Based SONOS Flash Memory Device With Improved Performance

In this paper, we report on the assessment of self-amplified silicon-oxide-nitride-oxide-silicon (SONOS) memory device architecture for sub-50-nm gate length (Lg) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (TSONOS) memory device has been analyzed. Results show that memory window (ΔW) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced AW can also be achieved in inversion-mode SONOS (ISONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for L
_g
varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at L
_g
= 25 nm and thus deteriorate the memory operation. However, SA T-SONOS at L
_g
= 25 nm achieves W ~ 6 V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories.