Optimization of ${V}_{\text{CE}}$ Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF

Collector-emitter voltage (
V
_CE
) plateau of the 500-V deep-oxide trench (DOT) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is investigated and optimized for the first time in this paper, aiming to reduce the turn-off loss (
E
_OFF
). The mechanism of
V
_CE
plateau is revealed by TCAD simulation. In conventional DOT SOI-LIGBT, the large number of stored carries in the silicon region beneath the DOT (Region I) hinders the extension of depletion layer and slows down
V
_CE
rising during turn-off, leading to a plateau phase. A novel DOT SOI-LIGBT with dual-controllable vertical field plates (CFPs) is proposed to shorten the
V
_CE
plateau. The dual CFPs are arranged in the DOT and their electric potentials (
V
_F1
and
V
_F2
) are controlled through the connection with scrolled resistive polysilicon filed plate. By adjusting
V
_F1
and
V
_F2
, the accelerated depletion and extraction of stored carriers in Region I can be realized, resulting in a short
V
_CE
plateau duration. The
V
_CE
plateau duration can be decreased from 156 ns for the conventional SOI-LIGBT to 60 ns for the proposed SOI-LIGBT with
V
_F1
= 0 V and
V
_F2
= 0.5
V
_CE
. The proposed DOT SOI-LIGBT achieves an EOFF 59.2% lower than the conventional DOT SOI-LIGBT at the same
V
_ON
of 2.96 V.