Modeling the Tunnel Field-Effect Transistor Based on Different Tunneling Path Approaches

In this paper, the effect of a choice of the tunneling path approach on electrical characteristics of the silicon tunnel field-effect transistor (TFET) is theoretically investigated with the use of a developed 2-D semiclassical numerical simulator and a nonlocal band-to-band tunneling generation model. Three different tunneling path approaches are defined and examined: horizontal path, maximum valence band gradient, and minimum tunneling distance. Double-gate (DG) and single-gate (SG) transistor structures are considered, and effects of the silicon body thickness and the gate-source overlap are investigated. The differently defined tunneling paths lead to significantly different on currents. It is shown that the minimum tunneling distance approach results in the highest tunnel current, whereas the horizontal path approach underestimates the current, especially for thick semiconductor body layers and the SG transistor structures. A choice of the tunneling path approach can be crucial for the accuracy of modeling the drain current of the TFETs.