Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC ${I}$ – ${V}$ Characterization

Deuterium (D
₂
) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (
$\mu $
) was extracted using the gate transconductance (
${g}_{m}$
) method. It was found that
$\mu $
was improved before and after D
₂
annealing. The interface trap density (
${D}_{\text {it}}$
) as well as the oxide trap density (
${N}_{\text {ot}}$
) in the poly-Si TFTs was quantitatively extracted using both conventional dc I–V characterization and analysis of low frequency noise (
LFN
). The profile of
${N}_{\text {ot}}$
along the depth direction was investigated before and after D
₂
annealing using
LFN
characteristics. It was confirmed that
${D}_{\text {it}}$
as well as
${N}_{\text {ot}}$
was reduced by the D
₂
annealing, resulting in a reduction in power spectral density and variation.