Degradation of a-InGaZnO TFTs Under Synchronized Gate and Drain Voltage Pulses

Instability of a-InGaZnO thin-film transistors is experimentally investigated under synchronized V
_g
and V
_d
pulses' stress. Degradation of the transfer characteristic in the forward measurement mode is much smaller than that in the reverse mode, if a typical drain bias of 5 V is applied. The degradation is found to depend on the equivalent dc stress time rather than the pulse transition edge. Larger pulse period and/or duty ratio of the voltage pulses cause more severe degradation. The degradation is affected by the recovery phenomenon, which occurs transiently when the pulsed stress is in the “OFF” phase, and enhanced by Joule heating-induced channel temperature rise. A degradation model is proposed, in which electrons' trapping occurs at the channel/gate oxide interface, while extra electrons' injection via thermal-assisted tunneling and interface defects' generation occurs within a narrow region near the drain, forming a potential barrier therein. The model explains the observed degradation satisfactorily, and the result is verified by a 2-D simulation.