A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET

In this paper, we have developed a physics-based compact model for surface potential and drain current for a dual gate source/drain (S/D) spacer-based silicon nanowire reconfigurable field-effect transistor (RFET). The models are derived by dividing the active region of the device into several portions based on positioning of the gates, spacers, and the metal-silicide Schottky junctions. A charge density expression is first developed and the quasi-fermi potentials for both electron and hole transport are found out by applying the principle of current continuity. Using these and further solving the 2-D Poisson's equation self consistently for various subregions of the device, the drain current and surface potential are modeled subsequently. The model includes the effects of drain voltage, nanowire radius, temperature and Schottky barrier height. The accuracy of the derived results is tested using 3-D numerical technology computer aided design simulations. The proposed model can be used to study the behavior of ambipolar FETs having S/D spacers for varying device dimensions and also can be utilized for the future design of memory devices and circuits using spacer-based RFETS.

I. Introduction

Due to the trend of continuous downscaling, the current CMOS technology is gradually reaching its ultimatum [1]–[12]. The thirst for next generation devices which are flexible as well as easy to handle is on a sharp rise. Silicon nanowire-based devices are widely studied nowadays in addition to their planar counterparts because of their wrap gated conduction channels, which make them promising candidates for ultrascaling in the subnanometer regime. Owing to its interesting geometry and associated device physics, it is possible for the device researchers to explore various new device concepts with an ultrathin body nanowire. One such promising future generation device platform is the ambipolar silicon nanowire technology, which can provide both n- and p-FET device operations by alternate biasing of the individual top-gates [2]–[8]. As a result, they can be employed to provide complimentary and reprogrammable CMOS operation with fewer numbers of transistors than usual [8]–[11]. Moreover, they also offer an alternative to the classical trend of scaling by increasing the number of functions per transistor instead of reducing the device geometry. The enhanced functionality of this device depends upon tuning the charge carrier injection into the nanowire channel through the proper selection of an external gate bias that ultimately couples to the sharp and highly sensitive NiSi₂/Si source/drain (S/D) Schottky junctions. If we want n-type operation, one of the gates is used to inject electrons (majority carriers) into the active region of the nanowire and the other gate is used to block holes (minority carriers). With an alternate biasing arrangement p-type operation can also be obtained. It also offers a simple fabrication principle through the conventional bottom-up approach, because in this case, an undoped silicon nanowire is mainly taken into consideration. Since the S/D Schottky contacts are metallic, they also reduce variability, fringe capacitances, and high access resistance [11]–[13], [19], [20].