Demonstration of a Novel Two Source Region Tunnel FET

A novel silicon-on-insulator (SOI)-based tunnel FET (TFET) with two source regions (TSRs) is proposed and investigated by Sentaurus simulation. The incorporation of the TSR in the SOI platform augmented the effective tunneling area between source–channel junctions and hence boosts the drive current of the device. To restrain the leakage current at a lower value, we have introduced an isolator oxide which avoids the direct coupling of the source and the drain. The typical figure of merit of any device is its
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
ratio, which is
$\sim {9} \times {10}^{ {10}}$
of our proposed structure. The impact of various device geometry variations has been studied and optimized accordingly through extensive simulation. We have also benchmarked our proposed TSR-TFET results with the modified L-shaped TFET, line tunneling-based TFET, and point tunneling-based TFET and procured better results over all the reference devices.