All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs

In this paper, we present a complete study of the drain and gate current local variability in high-k/metal gate-stack 14-nm fully depleted silicon-on-insulator CMOS transistors. A thorough experimental characterization of both drain and gate current mismatch was performed. In addition, we developed, for the first time, models of the drain and gate current mismatch, valid in all operation regions. Finally, we demonstrate the universal validity of our models through Monte Carlo simulations.