I. Introduction
Junctionless FETs (JL-FETs) were proposed in 2009 [1]. Unlike conventional MOSFETs with p-n junctions, JL-FETs could provide a simplified fabrication process flow. JL-FETs that possess homogeneous junctions have potential to be a candidate for the nanoscaled FinFETs. However, there are still several critical issues for JL-FETs, such as determining the proper channel doping concentra-tion [2]. JL-FETs with low-channel doping concentration can fully deplete carriers at OFF-state, but source/drain (S/D) series resistance is too high to boost the drive current. On the other hand, increasing the channel doping concentration for JL-FETs degrades the turn-OFF ability. Therefore, JL-FETs with additional S/D implantation were proposed to overcome the series resistance issues. The JL-FETs with S/D implantation are also called junctionless-accumulation-mode FET [3], [4].