A Novel ${{V}}_{\textsf {DSAT}}$ Extraction Method for Tunnel FETs and Its Implication on Analog Design

This brief investigates for the first time, a method to extract the value of saturation drain voltage for a tunnel FET. The saturation in output characteristics of a TFET is found to take place when the difference in conduction band energy (ΔE
_C
) of channel (E
_CC
) and drain (E
_CD
) is a few K
_B
T. As the drain voltage (V
_DS
) increases, it is found that the device initially enters in a soft saturation state and subsequently into deep saturation. For any given value of gate voltage (V
_GS
), the onset of soft and deep saturation happens for a constant difference in V
_GS
and V
_DS
. We propose a novel method to extract this voltage difference V
_GD
, which is explained using a phenomenological approach. We have also validated our results with published experimental data. It is found that the output resistance (R
_o
), transconductance (g
_m
), and intrinsic gain (g
_m
× R
_o
) increase when the device enters in a soft saturation and attain a maximum value in deep saturation regime. Furthermore, a common source amplifier biased in soft saturation is also demonstrated to have a comparable voltage gain and bandwidth to the one biased in deep saturation.