A Thin-Film Transistor With High Drain Current Induced by a Trap-Assisted Electric Double Layer

A thin-film transistor (TFT) structure is proposed, where high current operation at low gate voltage is obtained through creation of an electric double layer at the semiconductor/insulator interface. For an n-type transistor, the dipole layer consists of electrons accumulated in the channel and holes trapped in the insulator close to the interface. The dipole layer results in high gate capacitance even with larger insulator thicknesses resulting in low voltage operation. To enable charge/discharge of traps, the insulator is replaced by a semiinsulating layer that allows moderate amounts of gate current to flow; 2-D device simulation results are presented to illustrate and validate the proposed transistor concept. Evidence of trap assisted creation of higher gate capacitance and drain current are provided through experimental measurements on amorphous In-Ga-Zn-O TFTs with e-beam evaporated SiO
₂
gate dielectric.