A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates

Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise margin (NM) model for junctionless double-gate MOSFET working on subthreshold CMOS logic gate. The device parameters such as the thick silicon thickness, thick gate oxide thickness, high doping density, and short channel length can severely degrade the NM due to serious SCE. By contrast, both the small subthreshold slope η and the balanced transistor strength S can suppress the NM degradation more efficiently. The required minimum supply voltage Vdd,min for the subthreshold CMOS logic gate is derived by the criterion of the NM larger than thermal noise to ensure the correct logic gate operation. Being similar to drain-induced barrier lowering, allowable NM corresponding to the minimum channel length can also be uniquely controlled and determined by the scaling factor according to the scaling theory.