I. Introduction
The 3-D IC is paving a potential path toward More-than-Moore technologies, since it offers another dimension by stacking functional blocks vertically [1]. As a key component in 3-D IC, through-silicon via (TSV), which is a high aspect ratio vertical interconnect providing connectivity between active layers, has attracted a lot of research interests in the past decade [2]. Recently, a number of studies are devoted to the electrical modeling and fabrication technologies for TSVs [3]–[8]. For example, Xu et al. [4] proposed a comprehensive compact resistance–inductance–capacitance–conductance model for ground–signal (GS)-type TSVs, with the consideration of the MOS effects.